View ZR36015_72258.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ZR36015
PRELIMINARY
RASTER TO BLOCK CONVERTER
FEATURES
s s s s s Real Time Raster to/from Block Conversion 1/2 Decimation Processing in the Horizontal Direction 30 MHz Maximum Clock Rate Only Image in Preset Window is Converted Compatable with Zorans ZR36050 JPEG Coder and ZR36011 Color Space Converter s s s s s s Supports 1:0:0,4:2:2,and 4:1:1 data formats 100-pin plastic quad flat package (PQFP) TTL level Input/Output Synchronous data and controls Low power consumption: 0.45W (Typ.) CMOS circuit operating with a single 5V power supply
APPLICATIONS
s Image processing s Multi-media s Scanners s Image Storage s Image Capture
DESCRIPTION
The ZR36015 performes raster to/from block conversion for image compression and expansion applications, and it can be connected directly to the ZR36050 JPEG coder and the ZR36011 Color Space Converter. An image compression system can be easily constructed using the ZR36015 with the ZR35060 and ZR36011. The ZR36015 uses a double buffered external SRAM Strip Buffer to support raster to/from block conversion and block interleave. The maximum number of pixels that can be processed per line is 8K. The maximum number of lines that can be prcessed per image is 16K. These numbers vary according to the mode of operation. The ZR36015 supports 4:0:0, 4:1:1, and 4:2:2 data formats, and one half decimation in horizontal direction during compression. The maximum data transfer rate to the ZR36050 coder is 30 MHz. [The ZR36015 is fabricated with an advanced low-power CMOS technology, making it suitable for use in low-power, cost sensitive applications. The device is availiable in a 100 pin , Plastic Quad Flat Package (PQFP).]
Host Interface SPH WR RD ADD(1:0)
Internal Register Control CBSY
Raster/Block Address Generator
MWE MOE MADD(15:0) Memory Interface
8
PXDATA(15:0) CBUSY HEN VEN WINDOW BSY CLKCSC SPH RD WR ADD(1:0) SYSCLK RESET
MWE MOE
16
PXDATA(15:0)
1/2 Decimation
I/F
Selector
MDATA(15:0)
Pixel Interface
MADD(15:0)
16
Memory Interface
Sub Buffer
I/F
Pixel Interface HEN VEN WINDOW BSY CLKCSC Window Control
MDATA(15:0)
RESET SYSCLK Host Interface
2
8
BDATA(7:0) COE EOS STOP DSYNC Coder Interface
Interface Logic
I/F System Clock
DSYNC EOS STOP COE Coder Interface
BDATA(7:0)
System Reset
Figure 1. ZR36015 Block Diagram
ZORAN Corporation
Figure 2. ZR36015 Logical Pinout s
FAX (408) 986-1240 June 1993
s
1705 Wyatt Drive
s
Santa Clara, CA 95054
s
(408) 986-1314
This document was created with FrameMaker 4.0.4
PRELIMINARY
ZR36015
SIGNAL DESCRIPTION
Name PXDATA(15:0) Type1 B Function Pixel side data bus. Input for compression and output for expansion. High impedance during RESET or IDLE modes. When SPH is active (High), PXDATA(7:0) is controlled by the Host Interface. It will be high impedance except during a Host read access, in which case it will be driven. The state of PXDATA(15:8) follows that of PXDATA(7:0) in this case but is unused. Active High Horizontal enable signal (HDelay starts counting from the rise of HEN) Active High Verticle enable signal (VDelay starts counting from the rise of VEN) System clock (active on rising edge). Address output for the strip memory. Up to 64K x 16 bits of SRAM is addressable. Data bus for the strip memory. Memory A is assigned to MDATA(7:0), and Memory B is assigned to MDATA(15:8). Active Low: Write enable for the Strip Memory. Active Low: Output enable for the Strip Memory. Active Low: Sync. signal for 64 byte block of data. Output during compression and input during expansion. In compression, DSYNC marks the start of an 8x8 image data block and should appear as an output one SYSCLK cycle before the first image data of a block. During expansion DSYNC is input on SYSCLK before the first image data of a sample block. The width of DSYNC is one SYSCLK. (Connect directly to ZR36050 DSYNC signal). Active Low: Stop sending/receiving. During compression, this signal is an input which indicates that the CODEC is busy, and the ZR36015 should stop sending data. During expansion, this signal is an output indicating the ZR36015 is not ready to receive data, and for the CODEC to stop sending data. (Connect directly to ZR36050 STOP signal). Active Low: Signal indicates the end of each scan. Output during compression and input during expasion. In compression, EOS is output together with the last image data sample of the last block of each scan. In expansion, EOS is input together with the last image data sample of the last block of each scan. (Connect directly to ZR36050 EOS signal). Data bus interface with the Coder. Output for compression and input for expansion. High impedance during reset. Otherwise, the direction of the bus is determined by the COE input. (Connect directly to ZR36050 PIXEL(11:4) bus.) Address select for Host access to internal registers. Enabled when SPH is high. Active Low: Write strobe for Host loading of internal registers and tables. Data is writtern on the rising edge of WR. WR is enabled when SPH is high. Active Low: Read strobe for Host reading of internal registers and tables. RD is enabled when SPH is high. Active Low: CBSY indicates that the ZR36015 is not ready for the next strip of data. Coder bus output enable signal. HIGH for Compression Mode (enabling the output drivers for the CDATA bus, EOS signal and DSYNC signal. . LOW for Expansion mode (enabling the output drivers for the STOP signal). (Connect directly to ZR36050 COMP signal). Active Low: BSY is active when the ZR36015 is processing an image. Before setting hte GO bit in the Mode Register, BSY should be inactive. Clock output for ZR36011 Color Space Converter. Used to synchronize data transfers. Active High: Select host access to the ZR36015 via the PXDATA(7:0) data bus. Enables the WR, RD inputs. Active HIGH; Indicates active (windowed) image area. Asynchronous Active LOW reset. All bi-directional signals are tri-stated when this signal is active. After RESET , the ZR36015 will be in idle mode (GO bit cleared) and the PXDATA bus will continue to behigh impedance until the GO bit is set . Power terminal. Ground terminal.
HEN VEN SYSCLK MADD(15:0) MDATA(15:0) MWE MOE DSYNC
I I I O B O O B
STOP
B
EOS
B
BDATA(7:0)
B/Z
ADD(1:0) WR
I I
RD CBSY COE
I O I
BSY
O
CLKCSC SPH WINDOW RESET
O I O I
VDD VSS
-- --
1. I = Input, O = Output, B = Bidirectional, Z = High Impedance.
2
PRELIMINARY
ZR36015
FUNCTIONAL DESCRIPTION
The ZR36015 performs conversion between raster and block formatted data, with applications in image compression and expansion. It is designed to work with the ZR36050 JPEG Codec. Figure 1 is a block diagram of the ZR36015. The ZR36015 is a programmable device with an asynchronous Host Interface (WR,RD,ADD(1:0) which is enabled by the SPH input . Data is transferred between the Host and the ZR36015 internal Control Registers and configuration tables via the PXDATA(7:0) bus. Because PXDATA(7:0) is used to transfer data to/from the Host, and also for pixel data, an external buffer is required to prevent bus contention. The internal control registers of the ZR36015 consist of four registers which set the operating mode of the device and control the interface between the host and the configuration tables. The configuration tables are used to specify an active window within the region defined by the VEN and HEN inputs, and to count the actual number of lins that were processed. The ZR36015 interfaces to a pixel data bus PXDATA(15:0), which transfers 4:0:0, 4:1:1, or 4:2:2 formatted data. Transfer of data on the Pixel Bus is controlled by the Verticle Enable (VEN) and Horizontal Enable (HEN) inputs. During Compression, Pixel data can be optionally decimated by 2 in the horizontal direction. When the ZR36015 is interfaced to the ZR36011 "Color Space Converter", then it is recommended that the Clock for Color Space Converter (CLKCSC) output be connected to the input clock for the ZR36011. The ZR36015 supports a double buffered Strip Buffer SRAM architecture, with up to 64K 16 bit words. The Strip Buffer stores the image data in interleaved block format. Interleaved block formatted data is transferred between the ZR36015 and the ZR36050 over the BDATA bus. The ZR36015 can be directly interfaced with the ZR36050 JPEG Codec. Block transfers of data are controlled by the DSYNC, STOP, EOS, COE signals, with data being transferred on the BDATA(7:0) bus. These signals are connected directly to the ZR36050 DSYNC, STOP, EOS, COMP, and PIXEL(11:4) signals respectively. Overflows or underflows of the double buffered Strip Memroy are indicated by the CBSY output. The figure shows A/D and D/A conversion devices in between an image source/display and the ZR36011 (Color Space Converter). The bus between the ZR36011 and the D/A and A/D converterters is in 24 bit RGB format. In Compression mode the ZR36011 converts the RGB data into YUV (luminance/chrominance) data for more efficient compression. In Compression mode, the ZR36015 (Raster to Block Converter), converts the raster data into 8x8 blocks for processing by the ZR36050 JPEG Codec. The SRAM strip buffer stores 8 lines of data for conversion into block format. In Compression mode, the ZR36050 JPEG Codec performes JPEG compression on the block data, and transfers the compressed image over the system bus. In expansion mode, the process described above is reversed. The ZR36015 and ZR36050 devices are programmed via the system bus, and require minimal host intervention during the compression/expansion processes.
Image Source/Display
24 24
24
A/D Converter
24
D/A Converter Digital RGB
24 24
ZR36011 Color Space Converter Digital YUV ZR36015 Raster to Block Converter YCbCr ZR36050 JPEG Image Processor
16
SRAM Strip Buffer for Raster Block Conversion
System Bus
Figure 3. ZR36015 System Configuration Example
Control Registers
The ZR36015 has four Control Registers which allow the Host to set the mode of operation, and to initiate, terminate, and monitor
System Configuration Example
An example of the ZR36015 system configuration is given in Figure 3. This figure shows an image compression/expansion system which uses the ZR36011 (Color Space Converter) and the ZR36050 (JPEG Codec), in addition to the ZR36015.
3
PRELIMINARY
ZR36015
the status of compression or expansion prcesses. The four control registers are listed and described below. Table 1: Control Register Map
ADD(1:0) 00 01 10 11 Soft Reset Mode Register Address Pointer Register Configuration Register Tables Contents Host Access W R/W R/W R/W
s
s
Soft Reset Register (Write Only):
A Write to the Soft Reset Register will abort the current process, and put the ZR36015 in to the IDLE mode. The Soft Reset does not modify the internal registers of the ZR36015, except for the GO bit in the Mode Register (which is cleared). After a soft reset, the ZR36015 will be in the IDLE state. To start a new process, the GO bit in the Mode Register must be set by the Host.
Mode Register (Read/Write):
s
s
Set this bit to a `1' when interfacing the PIXDATA bus to the ZR36011 Color Space Converter, and to a `0' otherwise. Setting the CSC bit to a `1`, will modifies the pixel data internal delays during compression or expansion to match the delays in the ZR36011 Color Space Converter. A description of the modified pixel data delays is TBD. DCM: Select 1/2 Decimation Write Only) Set this bit to a `1' when selecting 1/2 decimation mode (for compression only). MOD(1:0): Pixel Data Mode Select These bits are set to determine the PXDATA bus to/from BDATA bus mode of operation. Table 3 shows the availiable combinations. EDC: Enclde/Decode select Selects either encode (EDC = `1'), or decode (EDC = `0') mode. GO: Process Go Trigger Bit (Write Only) Set to `1' to start ZR36015 processing. Prior to setting GO, the host must... 1) Make sure that the BSY bit is not set. 2) Set all processing parameters in the tables.
The table below shows the contents of the Mode Register.
Bit 0 Name GO Description Go: 0: ZR36015 IDLE 1: Set to indicate Encode or Decode process. 0: Decode mode selected 1: Encode mode selected Pixel data Mode Select (seeTable 2) Decimate data (Compression mode only). Active High. Select ZR36011 Color Space Converter Mode (Active High) Not Used Busy Flag (Active High)
When GO is set, the ZR36015 starts counting pixel elements from the rise of VEN and HEN. When [when is go reset?]
MOD(1:0) 00 01 10 PXDATA Format 1:0:0 4:2:2 4:2:2 4:1:1 BDATA Format 1:0:0 4:2:2 4:1:1 4:1:1
1
EDC
11
3:2
MOD(1:0)
Address Pointer Register(R/W):
4
DCM
5
CSC
6 7
BSY
This register is a pointer to the configuration tables and line count register. A write to the configuration table (ADD(1:0) = "0b11") will write to the table element indicated by the address pointer regstier. A read from the number of lines registers will access the register indicated by the address pointer register. The Address pointer Register is automatically incremented by one after a read or write with ADD(1:0) set to "0b11".
Configuration Register Tables(R/W):
The definition of these bits is given below: s BSY: Busy Flag (Read Only) Active High: Indicates that the ZR36015 is busy performing an encoding or decoding process. The next process should not be started until the current process completes (indicated by the ZR36015 clearing this bit). The BSY flag is set to `1' immediately after the GO bit is set. The BSY flag is cleared when the processing for an image is complete and the ZR36015 is ready for the next "GO". Before setting the "GO" bit (defined later in this section), the host should check that the Busy Flag is `0`, indicating that the previous process has completed. s CSC: Select ZR36011 Color Space Converter (Write Only)
The contents of the Configuration Table are shown in the below. The fields of the Configuration Table are defined below and in Figure 5. s HDelay(12:0): Horizontal delay in number of pixel elements before active window. The setting range for WDelay(12:0) is 0 to 8191. s HWidth(14:0): Horizontal width of the active image area. The setting range for Width(14:0) is up to 8191 for. s VDelay(12:0):Verticle delay in number of pixel elements before active window. The setting range for HDelay(12:0) is 0 to 8191.
4
PRELIMINARY
ZR36015
s VHeight(12:0):Verticle height of the active image area. The maximum setting for Height(12:0) is 8191. Setting Height(12:0) to `0' in encode mode, lets the Height of the active image area be determined by the non-active point of VEN.
Address Pointer Value 0 1 2 3 4 5 6 7 8 9 Window Setting Value HDelay(7:0) HDelay(12:8)1 HWidth(7:0) HWidth(14:0)1 VDelay(7:0) VDelay(12:8)1 VWidth(7:0) VWidth(13:8)1 Number of Lines(7:0) Number of Lines(13:8)1
Operating States
The ZR36015 has four Operating States; Reset, Idle, Compression and Expansion.
Reset State
While the RESET input is asserted, the ZR36015 is in the Reset State. In this state the PXDATA and BDATA busses are high impedance, and the DSYNC, STOP, EOS signals are high impedance. After a RESET, the ZR36015 will be in the IDLE state.
Idle State
After a Soft RESET, or after the RESET input signal has been applied, or at the end of a compression or expansion process, the ZR36015 will be in the IDLE state. In the IDLE state, no active processing is taking place, and the PXDATA bus is high impedance (the bus drivers for the Coder Interface are controlled by the COE signal). While in the IDLE state, the ZR36015 Configuration Register Tables can be loaded with the values to select the desired active image area. Also, the Mode Register is loaded with the desired Mode of operation, and the number of lines table can be read To leave the IDLE state and enter one of the processing states (compression or expansion), the GO bit in the Mode registe is set.
1. Assigned to LSB's of PIXDATA(7:0)
HEN
Enable Area
VDelay
Compression
When the GO bit is set to "1", and the EDC bit equals "1", then the ZR36015 enters the Compression State. Setting the GO bit results in the BSY bit in the mode register being set. Once the GO bit is set, then on the falling edge of the Verticle Sync Signal (VEN), the BSY output signal will be set. The BSY bit (and output signal) will stay set until the end of the Compression process. The hardware can monitor the BSY signal, to determine when the Compression process has completed. Note that the GO bit must be set at least three SYSCLK cycles before the VEN goes from High to Low (see figure ???). Following the above, the ZR36015 monitors the VEN input to detect the transiton of VEN from low to high. This indicates the beginning of the image to be processed The next VDelay lines of data are ignored in order to reach the "active image area". Then the next VWidth lines of data are processed. The HEN input synchronizes the line by line transfers of data into the ZR36015. On the rise of HEN, the next HDelay pixels are ignored in order to reach the "active image area". Then the next HWidth pixels are procesed.
VEN
Acitve Image Area
HDelay
HWidth
Figure 4. Active Image Area
Number of Lines Table:
The Number of Lines Table holds the number of lines processed in encoding by the ZR36015.
VWidth
5
PRELIMINARY
ZR36015
The MOD(1:0) bits in the Mode Register determine the format of the data on the PXDATA bus, and the DCM bit determines if decimation is performed. After the last of the data in the "Active Image Area" has been converted to Block format and transferred to the Coder (as indicated by the EOS output), the GO bit and the BSY bit (and BSY signal) are cleared and the ZR36015 enters the IDLE state. In order to compress a sequene of images, the GO bit must be set for each image. However, the table values do not have to be re-initialized for each image. PXDATA bus. Once host access is selected, the WE and RD signals initiate the writing and reading of data (using the PXDATA bus), to locations specified by the ADD(1:0) inputs. Since the Host and image source share PXDATA(7:0), an external bidirectional buffer is required on PXDATA(7:0) in order to avoid bus contention. The ADD(1:0), RD, and WR inputs are ignored when Host Access is not selected by SPH. The table below shows the addressing of the internal control registers by the ADD(1:0) address inputs.
Pixel Bus Formats
The Pixel Bus "PXDATA(15:0), is divided into two bytes. PXDATA(15:8) is always used to represent the Y data, while PXDATA(7:0) is always used to represent the UV data. The data formats of PXDATA are according to the setting of the MOD(1:0) bits in the Mode Register. Table 2 and 3 show the format of PXDATA bus for each mode. Table 2: Pixel Bus Data Format (Mode 3)
PXDATA PXDATA (15:8) PXDATA (7) PXDATA (6) 1st Y1 (7:0) U1 (7) U1 (6) V1 (7) V1 (6) - 2nd Y1 (7:0) U1 (5) U1 (4) V1 (5) V1 (4) - 3rd Y1 (7:0) U1 (3) U1 (2) V1 (3) V1 (2) - 4th Y1 (7:) U1 (1) U1 (0) V1 (1) V1 (0) -
Expansion
When the GO bit is set to "1", and the EDC bit equals "0", then the ZR36015 enters the Expansion State. Setting the GO bit results in the BSY bit in the mode register being set. Once the GO bit is set, then on the falling edge of the Verticle Sync Signal (VEN), the BSY output signal will be set. The BSY bit (and output signl) will stay set until the end of the Expansion process. The, to determine when the Expansion process has completed. Note that the GO bit must be set at least three SYSCLK cycles before the VEN goes from High to Low (see figure ???). Following the above, the ZR36015 monitores the VEN input to detect the transition of VEN from low to high. This indicates the beginning of the time interval when the image is to be output to the PIXEL bus. The ZR36015 waits VDelay lines before putting the first line of decoded data out to the PIXDATA bus. The HEN input synchronized the line by line transfers of data to the PXDATA bus. On the rise of HEN, the ZR36015 waits HDelay SYSCLKs until outputting the decoded line of pixels (HWIDTH of them) on the PXDATA bus. The MOD(1:0) bits in the Mode Register and the data in the Configuretino Tables, must match the format and size fo the data being decodced by the ZR36050. The DCM bit is not used in expansion. After the last of the data in the "Active Image Area" has been transmitted to the PXDATA bus, the GO bit and the BSY bit (and BSY signal) are cleared, and the ZR36015 enters the IDLE state. In order to expand a sequence of images, the GO bit must be set for each image. However, the table values do not have to be reinitialized for each image.
PXDATA (5) PXDATA (4) PXDATA (3:0)
Table 3: Pixel Bus Data Format (Modes 0, 1, 3)
Format (1:0:0) PXDATA
PXDATA (15:8) (Y) PXDATA (7:0) (UV)
1st Y0 2nd Y1
(4:2:2)
1st Y0 2nd Y1 1st Y0
(4:1:1)
2nd Y1 3rd Y2 4th Y3
-
-
U0
V0
U0 (7:6) V0 (7:6)
U0 (5:4) V0 (5:4)
U0 (3:2) V0 (3:2)
U0 (1:0) V0 (1:0)
PXDATA Syncronization Clock Frequency:
The input and output of data on PXDATA(15:0) are carried out in synchronization with the clock signal of SYSCLK for mode 0, or SYSCLK/2 for modes 1, 2 and 3. Table 4 shows the PXDATA bus sync clock frequency for each of the modes of operation.
System Interface
The SPH input is used to select host access to the ZR36015, (set SPH to `1'). Host access for read/write of the ZR36015's control registers is carried out using the system interface pins (RD,WR, and ADD(1:0)), in addition to the lower 8-bits of
6
PRELIMINARY
ZR36015
Table 4: PXDATA Bus Sync Clock Frequency
MOD (1:0) 0 (00) 1 (01) 2 (10) 3 (11) Pixel Side Format (1:0:0) (4:2:2) (4:2:2) (4:1:1) Coder Side Format (1:0:0) (4:2:2) (4:1:1) (4:1:1) PXDATA Bus Sync Clock Freq.1 SYSCLK SYSCLK/ 2 SYSCLK/ 2 SYSCLK/ 2
VEN Active Image Area BSY EOS Output
unknown number of lines. At the end of processing, the "Number of Lines" register will contain the number of lines that have been processed. Figure 7 illustrates the "active image area" for this special case.
HEN
1. The sync clock freq. of the coder bus side is SYSCLK in all modes.
The data seen on the Pixel Bus during Compressoin is shown in Figure 5.
PIXEL PROCESSING TIMING
The leading edge of the frame is identified by the fall of VEN (after the GO bit is set). Tge VDelay is counted from the following rise of the VEN input. The HDelay is counted from the rise of the HEN input. The HEN and VEN signals must remain high at least until the end of the active image area (as defined by the Configuration Register table). HEN must conform to either A or B in Figure 8. Within the image area defined by the VEN and HEN signals, is the "Active Image Area", which is determined by the HDelay, HWidth, VDelay, and VWidth values in the configuration table. Pixel processing is performed only on those pixels which lie in the active image area defined in Figure 4. The width and height of the active image area are determined by the "HWidth" and "VHeight" values in the configuration register table. If VWidth is set to zero (a special case), then lines will continue to be processed for as long as VEN remains high (maximum of 8K lines). This feature allows processing of frames with an
SYSCLK HEN MOD[1:0] = 0 CLKCSC PXDATA (15:8) MOD[1:0] = 1, 2 CLKCSC PXDATA (15:8) PXDATA (7:0) MOD[1:0] = 3 CLKCSC PXDATA (15:8) PXDATA (7:6) PXDATA (5:4) Y1 U11 V11 Y2 U12 V12 Y3 U13 V13 Y4 U14 V14 Y5 U21 V21 Y6 U22 V22 Y7 U23 V23 Y1 U1 Y2 V1 Y3 U2 Y4 V2 Y5 U3 Y6 V3 Y7 U4 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14
Figure 6. Pixel Processing Image Area
HEN
VEN
EOS Output
Figure 7. EOS Asertion
Figure 5. Functional Timing Chart - Pixel Bus Side
7
NOL
Active Image Area
PRELIMINARY
ZR36015
HEN A B
A > 48 SYSCLK Cycles B is an even number of SYSCLK cycles HEN signal must conform to eather a or B
Figure 8. Setting of HEN Timing
Window Output Signal
The WINDOW output (active high) is aligned with the PDATA bus, identifying the pixels which correspond to the active image area. Figure 5 shows the functional timing for the window signal for the case where Mode=0, and HDelay = 0 or HDelay = 3. The Window signal is set "HDelay" pixels after the rise of HEN, and goes inactive "HWidth" pixels later. The timing for the WINDOW signal is identical for both compression and expansion modes.
SYSCLK HEN N = HDelay+HWidth PXDATA ex. MOD = 0 WINDOW ex. HDelay = 3 WINDOW ex. HDelay = 0 012345 HDelay HWidth HWidth N
Figure 9. Example of Window Output Timing
Line Counting
The ZR36015 counts the number of lines that were processed during encoding mode, and stores this number in the "number of lines" registers defined in Table 5. When "VHeight" is set to zero, the number of lines processed is dependent on the duration of the VEN signal. If the duration of the VEN signal does not correspond to an active image area with a number of lines that is a multiple of 8 (for modes 0,1,3) or a multiple of 16 (mode 2) then the number of lines is rounded up to the nearest multiple of 8(16). This feature ensures blocks of data that are compatible with JPEG image compression algorithms. If the number of lines being processed exceeds 8192, then the ZR36015 terminates the processing after processing 8192 lines.
"BUSY" Bit and Busy Signal Timing
The BSY (Busy) bit in the Mode Register is set to `1' (active) when the Go bit is aserted. When the ZR365015 finishes processing the data in the active image area, it clears the BSY and GO bits and the BSY signal. The BSY signal follows the BSY bit when VEN falls.
Setting GO
The GO bit in the Mode Register is set in order to begin processing of an image. Before setting the GO bit, the ZR36015`s Mode Register and Table values should be configured for the desired operation, and the BSY bit (in the Mode Register) should be checked to insure that it is not set. If the BSY bit is set, this indicates that the previous process has not completed, and so the ZR36015 is not ready to start a new process. If the BSY bit is not set, then the ZR36015 is free to begin a new process. The BSY signal can be monitored to determine when the previous process is complete. When the GO bit is set, then the ZR36015 will respond to the next VEN that is sees. The GO bit must be set at lease 3 SYSCLK cycles before the trailing edge of VEN in order to respond to the next active high pulse of VEN. If the GO bit is not set at least 3
8
PRELIMINARY
ZR36015
SYSCLKs before the trailing edge of VEN, then the following VEN signal (active high) will be ignored, and the VEN pulse after that will be processed.
GO VEN Line BSY (signal) BSY (bit) At least 3 SYSCLKS VDelay VWidth Delay of Internal Processing
Figure 10. Relationship of BSY Terminal and BSY Flag and GO Bit
DECIMATION
Horizontal Decimation of data by a factor of 2 is supported for the ZR36015. This allows for the reduction of the volume of data being stored in the Strip Buffer (and sent out over the BDATA bus) by half. The tables below shows how data is decimated for each mode.
Decimation Mode 0 (4:0:0) Mode 1 (4:2:2) Y0 Y0 U0 Mode 3 (4:1:1) Y0 Y1 Y1 V0 Y1 Y2 Y2 U2 Y2 Pixel Elements Y3 Y3 V2 Y3 Y4 Y4 U4 Y4 Y5 Y5 V4 Y5 Y6 Y6 U6 Y6 Y7 Y7 V6 Y7
U0/V0
U4/V4
During expansion there is no interpolation mode for the data (except as described below for mode 2). In mode 2, the data is decimated horizontally as shown above for mode 1. But in addition, the UV data for every other line (starting with the second line) is dropped. The figure below shows this case.
Decimation Mode 2 (1st line) Mode 2 (2nd line) Y0 U0 Y0 U0 Y1 V0 Y1 V0 Y2 U2 Y2 U2 Pixel Elements Y3 V2 Y3 V2 Y4 U4 Y4 U4 Y5 V4 Y5 V4 Y6 U6 Y6 U6 Y7 V6 Y7 V6
During Expansion in mode 2, the UV data for the 1st line is replicated to replace to corresponding UV data for the second line. Note that the MCU for mode 2 will be H=2, V=2.
Sub-Buffer and Strip Buffer Interface
Figure 12 shows the Sub-Buffer Interfaces between the Pixel Data, the Coder Data, and the double buffered Strip Memory. The Strip Memory Interface can perform a 16-bit read or write on every SYSCLK cycle. In order to keep up with the required data throughput, the Pixel Data and Coder Data Sub-Buffers each must be able to perform a 16-bit read or write to the Strip Memory on every other SYSCLK cycle. Therefore the Strip Memory Interface is shared between the Pixel Data, and Coder Data Sub-Buffers, with each Sub-Buffer accessing the Strip Memory on alternate SYSCLK cycles. Figure TBD shows the timing for alternate read and writes to the Strip Memory. The Pixel Data Sub-Buffer performs conversion of the data between the PXDATA Bus and the Strip Memories. (The A Memory stores the data for all the even pixels, and the B Memory stores the data for all the odd pixels; (see the section on Strip Memory Format).
9
PRELIMINARY
ZR36015
The Coder Data Sub-Buffer performs the conversion of the data between the Strip Memories and the Coder Data Bus. During Compression, pixel data is transferred from the PXDATA Bus to the Strip Memories, and data from the Strip Memories is transferred to the Coder Data Bus. During Expansion, Coder data is transferred to the Strip Memories, and data from the Strip Memories is transferred to the Pixel Data Bus. Figure TBDX7 shows the timing for the data and the control signals for the Strip Buffer Interface. Note that reads and writes to the Strip Memory are asynchronous to one another, in that either can continue to occur (on alternate SYSCLK cycles) independently of whether or not the other side is ready to transfer data. The only restriction is that a strip buffer must be emptied (filled) before its time to switch sides (or else the CBSY signal becomes active (see section TBD)
Strip Buffer
In Compression, the raster format data is read into the Strip Buffer and stored in interlaced JPEG Block format in the Strip Buffer. This data is then read out to the Coder Data Bus in interlaced Block format for compression by the JPEG CODEC (ZR36050). In Expansion, the operation is reversed. For modes 0,1 and 3,the Strip Buffer is filled with the data from 8 lines. For mode 2, data from 16 lines is stored in a Strip Buffer. The Strip Buffers are composes of an A and B side. The A side stores the even pixel data and the B side stores the odd pixel data. Figure 12 shows the A and B sides to the Strip Buffers. In order to provide double buffering (two strip buffers), the A and B memories are separated into high and low address spaces. The high address space of the A and B Memories is indicated by the A' and B' shown in the figure below. The starting address of A' and B' is determined by the mode of operation for the ZR36015 and whether decimation is being performed (see the section on Strip buffer Capacity).
MD0205DN Pixel Data Side
16
Strip Memory
ZR36015 Sub Buffer A' A B' B
16 16 16
8
8
Coder Data Side
Figure 11. Double-Buffer Configuration
10
PRELIMINARY
ZR36015
CODER BUSY SIGNAL (CBSY)
Before changing over from the A/B face to the A'/B' face of from the A'/B' face to the A/B face the CBSY signal must not be active. The CBSY signal is active under the following conditions. 1. In compression, when all of the pixel data for the active window have been written to the Strip Memory, then CBSY will be asserted if the Coder has not yet read out all data from the other side of the Strip Memory Buffer. 2. In expansion, when all of the pixel data for the current frame has been read out of one face of the double buffered Strip Memory, and the Coder has not yot filled the other side of the buffer with data for the next frame. In either Compression or Expansion, if CBSY is set, then the first HEN signal (for the next strip) should not be asserter until the CBSY signal becomes inactive. Factors which can alleviate system problems which are caused by CBSY, are the use of decimation and/or the reduction of the "active image area".
CONDITIONS FOR CBSY IN ENCODING MODE
The following sections describe the CBSY signal in relation to the timing for loading and unloading the strip memory. Examples are given for the encoding and for the decoding modes. The Strip Memory is double buffered, with one buffer being represented by the A,B memories, and the othre buffer represented by the A',B' memories (see figure TBD). For the purpose of the following discussions, we assume that we start loading to the AB side of the Strip Buffer, and then load the A'B' side of the strip buffer (see references to AB,A'B' in figures TBD-TBD).
Encoding Examples of CBSY Timing
Example #1 : No CBSY
Figure 12 shows an example in encoding mode, where the CBSY is not issues. Referring to Figure 12, following sequence of events occur... 1. HEN goes HIGH, (indicating the start of the last line of a strip. The ZR36015 begins to count HDelay in order to ingnore the first HDelay pixels of the line. 2. DSYNC active indicates that data for Strip Buffer AB (previously loaded) is being unloaded to the Coder Bus. 3. The ZR36015 finishes counting HDelay; data for Strip Buffer A'B' continues to be loaded from the Pixel bus. 4. Readout of data from the A'B' side of the strip buffer is complete. The ZR36015 checks to make sure that the AB side of the Strip Buffer is full before switching sides to begin reading data from the AB side to the Code Buffer. In Example 1, The first DSYNC for the next strip is not issues immediately because the A'B' side of the Strip Buffer is still being loaded. 5. The writing of a strip to the A'B' side of the Strip Buffer is complete. At this time the Coder side switches, and data from the A'B' side of the strip buffer starts to be read out to the Coder interface, as indicated by the active DSYNC signal. In Example 1, no CBSY was generated because when the strip being loaded into the A'B' side of the Strip Buffer was completed, the AB side of the code buffer was already empty and the Pixel Side was able to switch to the AB side immediately in order to begin writing the next strip. We assummed in Example 1 that STOP was not active, otherwise new DSYNCs would not be issued (i.e. the ZR36015 would not write data to the ZR36050 Codec) until the STOP signal became inactive.
11
PRELIMINARY
ZR36015
HEN NAX
Delay to Memory Write1
PXDATA Bus
PAX
Check if all contents of the coder side buffer have been read out. Check if all contents of the pixel side buffer have been entered. Buffer selection point2
Write to Strip Buffer PAX
PAX
Read From Strip Buffer
The pixel side buffer is monitored as required3
DSYNC/ISYNC 1. 2. 3. See table TBD for "Delay to Memory Write". The "Buffer Selection Point" happens at the completion of writing a strip (???? line), and indicates when the ZR36015 switches strip buffer sides to read this new strip. When a complete strip has been written, then the 1st DSYNC for this strip will be asserted (assuming that STOP is not active).
Figure 12. Example of Double-Sided Buffer Selection Timing - In Encoding (No CBSY)
Example #2: Short CBSY
Figure 13 shows an example in encoding mode, where the CBSY is issued for a short period (i.e., CBSY becomes inactive before the beginning of input for the next strip). 1. HEN goes HIGH, indicating the start of the last line of a strip. The ZR36015 begins to count HDelay in order to ingnore the first HDelay pixels of the line. 2. The ZR36015 finishes counting HDelay; data for Strip Buffer A'B' starts to be loaded from the Pixel bus. 3. DSYNC active indicates that data for Strip Buffer AB (previously loaded) continues to be unloaded to the Coder Bus. 4. The writing of a strip to the A'B' side of the Strip Buffer is complete. At this time the ZR36015 checks to see if the datat from AB has been unloaded. In example 2, AB is still in the process of being unloaded, so the CBSY signal is asserted to indicate the the ZR36015 is not ready to accept more input data from the Pixel side. Readout of data from the AB side of the strip buffer is complete. Now two things happen. First, the ZR36015 detects that data is already availiable in the A'B' side of the Strip Buffer, and so it continues to assert DSYNCs, indicataing that the A'B' side is now being unloaded to the Coder Bus. Second, the CBSY signal becomes inactive, indicating that the AB side of the strip buffer is now empty and that data from the Pixel Bus can be loaded into the AB side.
HEN NAX PAX
Check if all contents of the coder side buffer have been read out.
PXDATA Bus
Write to Strip Buffer
PAX
Buffer selection point Check if all contents of the pixel side buffer have been entered.
Read From Strip Buffer
PAX
The coder side buffer is monitored as required
CBSY
DSYNC 1. 2. When CBSY is outputted at the timing as shown above (completed within one line), the following oine is not ignored. The timing of CBSY when the line is ignored is as shown below.
Figure 13. Example of Double-Sided Buffer Selection Timing - In Encoding (Short CBSY)
Example #3: CBSY active when HDelay + HWidth is set to the maximum period of HEN
Figure 14 shows an example in encoding mode, where the HDelay + HWidth is set to the maximum perion of HEN. Because of this, the CBSY can become active after the HEN for the 1st line of the next strip becomes active. 1. HEN goes HIGH, (indicating the start of the last line of a strip. The ZR36015 begins to count HDelay in order to ingnore the first HDelay pixels of the line.
12
PRELIMINARY
ZR36015
2. DSYNC active indicates that data for Strip Buffer AB (previously loaded) continues to be unloaded to the Coder Bus. 3. The ZR36015 finishes counting HDelay; then data for Strip Buffer A'B' continues to be loaded from the Pixel bus. 4. The writing of a strip to the A'B' side of the Strip Buffer is complete. At this time the ZR36015 checks to see if the datat from AB has been unloaded. In example 3, AB is still in the process of being unloaded, so the CBSY signal is asserted to indicate the the ZR36015 is not ready to accept more input data from the Pixel side. But before CBSY is asserted, the next HEN signal (for the first line of the next strip) becomes active. HEN has become active because the CBSY signal was not asserted in time to stop it. This is due to the HDelay+HWidth values being the maximum (length of HEN). Also, we've assumed that the low period between HENs is minimal. In example 3, line 8n+1 will be ignored (lost) due to the CBSY signal. The ZR36015 will begin processing the next new input line after CBSY is de-asserted.
HEN 8n PXDATA Bus NAX
Delay of internal processing
8n+1
PAX
Check if all contents of the coder side buffer have been read out.
Write to Strip Buffer
PAX
Buffer selection point
Check if all contents of the pixel side buffer have been entered.
Read From Strip Buffer
PAX
The coder side buffer is monitored as required
DSYNC/ISNYC
CBSY 1. If PAX + NAX is set to the maximum effective period of HEN as shown above, CBSY may be active on a line following the 8n line (16n line depending on the mode) for the reason of internal delay. In this case, the processing of the line is started in MD0205, and finished when CBSY is active. In case of the above timing chart, MD0205 ignores the 8n+1 line, waits until CBSY becomes non-active and resumes processing from the rise of next HEN (8n+2 line).
Figure 14. Example of CBSY Timing - In Encoding (HDelay + HWidth = Width of HEN)
Example #4: Long CBSY, New lines continue to come in
Figure 15 shows an example in enoding mode, where the CBSY signal is active for a long period (this could be the result of the STOP signal being active for a long period). Also in this example, new lines continue to be input into the ZR36015 (as indicated by the HEN signal). In example #4, lines 8n+1 and 8n+2 will be ignored (lost), and processing will continue with line 8n+3. For system which must not loose lines of data, the new lines of data must be held up and only input after CBSY becomes inactive.
HEN 8n PXDATA Bus NAX PAX 8n+1 8n+2 NAX
Buffer selection point
8n+3 PAX
Write to Strip Buffer
PAX
Check if all contents of the coder side buffer have been read out. Check if all contents of the pixel side buffer have been entered.
Read From Strip Buffer
The coder side buffer is monitored as required
CBSY
DSYNC/ISNYC 1. If the processing at the coder side is substantially delayed and CBSY is outputted for a long period of time as shown above, all lines which cover CBSY are ignored. Accordingly, in case of the above timing chart, the 8n+1 line and the 8n+2 line are ignored and the processing is started from the 8n+3 line.
Figure 15. Example of CBSY Timing
13
PRELIMINARY
ZR36015
Decoding Examples of CBSY Timing
Example #5 BUSY in Decoding Mode. Three examples for Decoding, Figure 24, E2, E3.
N1 DSYNC
BDATA (7:0)
64
1
2
3
4
5
6
7
8
62
63
64
1
The pixel side buffer is monitored as required
2
3
4
Delay of internal processing
Write to Strip Buffer
1 block data Check if all contents of the pixel side buffer have been read out.
Buffer selection point
Read From Strip Buffer
Final line data of the readout side buffer Delay of internal processing
PXDATA
PAX
Check if all contents of the coder side buffer have been entered.
STOP
Figure 16. Example of Double-Sided Buffer Selection Timing - In Decoding
N1 DSYNC
BDATA (7:0)
64
1
2
3
4
5
6
7
8
62
63
64
1
2
3
4
5
6
7
8
9
Delay of internal processing
Buffer selection point 1 block data Check if all contents of the coder side buffer have been entered.
Write to Strip Buffer
Read From Strip Buffer
Final line data of the readout side buffer
Check if all contents of the pixel side buffer have been read out.
Delay of internal processing
PXDATA
PAX
The coder side buffer is monitored as required
CBSY
Figure 17. Example of Double-Sided Buffer Selection Timing - In Decoding
14
PRELIMINARY
ZR36015
N1 DSYNC
BDATA (7:0)
64
1
2
3
4
5
6
7
8
62
63
64
Buffer selection point
1
2
3
4
5
6
Delay of internal processing
Write to Strip Buffer
1 block data Check if all contents of the pixel side buffer have been read out. Check if all contents of the coder side buffer have been entered.
Read From Strip Buffer
Final line data of the readout side buffer
PXDATA
PAX
Delay of internal processing The coder side buffer is monitored as required
CBSY
STOP
Figure 18. Example of Double-Sided Buffer Selection Timing - In Decoding
Strip Buffer Memory Format
Two SRAMs form a strip buffer. The 16-bit wide strip buffer is divided into 2 areas at point * HWidth. Where: = K * L * HWidth * D
Low Memory Memory A (lower 8 bits) Memory B (Upper 8 bits)
Address 0
High Memory Read Area (Write Area) Read Area (Write Area)
Write Area (RD Area) Write Area (RD Area)
Address = * HWidth
An example of the amount of data stored in the strip buffer for each component of an active region of 704 x 240 is given in Figure 16.
15
704 240
PRELIMINARY
ZR36015
1 Field
MOD1:0 = 01
MOD1:0 = 10
MOD1:0 = 11
720 240 240 240 240 240 240 240
360
360
720
360
360
720
180 240
180 240
Y
U
V
Y
U
V
Y
U
V
DCM = 0
DCM = 1
DCM = 0
DCM = 1
DCM = 0
DCM = 1
720 240 240 240 240 240 240 240 240
360
360
360
180
180
720
240
360 120
360 120
360
180 120
180 120
720
180 240
180 240
360 240
90 240
90 240
Y
U
V
Y
U
V
Y
U
V
Y
U
V
Y
U
V
Y
U
V
Figure 19. Mode Selection Table
16
PRELIMINARY
ZR36015
Component interleave sequence for blocks of data (as seen on the code data bus) MODE1:0 = 00 MODE1:0 = 01 MODE1:0 = 10 MODE1:0 = 11 Y0 Y00 Y00 Y00
8
Y1 Y01 Y01 Y01
8
Y2 U00 Y10 Y02
8
Y3 V00 Y11 Y03
Y4 Y02 01U0 U00
8
Y5 Y03 01V0 V00
U01 Y02 Y04
V01 Y03 Y05
Y12 Y06
Y13 Y07
01U1
01V1
U01
V01
MODE = 01 8
Y00
8
Y01
8 8
U00
8
01U0
V00
8 8
01V0
MODE = 10
8 8
Y00 Y10
8
Y01 Y11
8 8
8
8
8
8
8
MODE = 11 8
Y00
Y01
Y02
Y03
U00
V00
Note: YX notation indicates the "x"th block of data for component Y
Figure 20. Memory Format - Write Area
Pixel Data Memory Data <15:8> Memory Data <7:0> Strip Memory
0Y 0
0Y 1 0Y 0 0Y 1
0Y 2 0Y 2 0Y 3
0Y 3 0Y 4 0Y 5
0Y 4 0Y 6 0Y 7
0Y 5 0Y 8 0Y 9
A Memory
MADD 0 $20 $40
0
0Y 0 0Y 8 0Y16
1
0Y 2 0Y10 0Y18
2
0Y 4 0Y12 0Y20
3
0Y 6 0Y14 0Y22
4
1Y 0 1Y 8 1Y16
5
1Y 2 1Y10 1Y18
1B
6Y 6 6Y14 6Y22
1C
7Y 0 7Y 8 7Y16
1D
7Y 2 7Y10 7Y18
1E
7Y 4 7Y12 7Y20
1F
7Y 6 7Y14 7Y22
1st Block 2nd Block 3rd Block
1st Line Data
2nd Line Data
6th Line Data
7th Line Data
B Memory
MADD 0 $20 $40
0
0Y 1 0Y 9 0Y17
1
0Y 3 0Y11 0Y19
2
0Y 5 0Y13 0Y21
3
0Y 7 0Y15 0Y23
4
1Y 1 1Y 9 1Y17
5
1Y 3 1Y11 1Y19
1B
6Y 7 6Y15 6Y23
1C
7Y 1 7Y 9 7Y17
1D
7Y 3 7Y11 7Y19
1E
7Y 5 7Y13 7Y21
1F
7Y 7 7Y15 7Y23
1st Block 2nd Block 3rd Block
Note: aYb notation indicates the Y component of the pixel element in row "a" and column "b".
Figure 21. Memory Format - MODE 1:0 = 00
Pixel Data <15:8> Pixel Data <7:0> Memory Data <15:8> Memory Data <7:0> Strip Memory MADD 0 $20 $40 $60 $80 0
0Y 0 0Y 8 0U 0 0V 0 0Y16 0Y 0 0Y 1 0Y 0 0U 0 0Y 2 0Y 3 0Y 1 0V 0 0Y 4 0Y 5 0Y 2 0U 1 0Y 6 0Y 7 0Y 3 0V 1 0U 0 0U 1 0Y 4 0U 2 0U 2 0U 3 0Y 5 0V 2 0V 0 0V 1 0Y 6 0U 3 0V 2 0V 3 0Y 7 0V 3 0Y 8 0Y 9 0Y 8 0U 4 0Y10 0Y11
Data Sequence on Pixel Bus
Data Sequence on Memory Data Bus
1
0Y 2 0Y10 0U 2 0V 2 0Y18
2
0Y 4 0Y12 0U 4 0V 4 0Y20
3
0Y 6 0Y14 0U 6 0V 6 0Y22
4
1Y 0 1Y 8 1U 0 1V 0 1Y16
5
1Y 2 1Y10 1U 2 1V 2 1Y18
6
1Y 4 1Y12 1U 4 1V 4 1Y20
19
6Y 2 6Y10 6U 2 6V 2 6Y18
1A
6Y 4 6Y12 6U 4 6V 4 6Y20
1B
6Y 6 6Y14 6U 6 6V 6 6Y22
1C
7Y 0 7Y 8 7U 0 7V 0 7Y16
1D
7Y 2 7Y10 7U 2 7V 2 7Y18
1E
7Y 4 7Y12 7U 4 7V 4 7Y20
1F
7Y 6 7Y14 7U 6 7V 6 7Y22
A Memory
1st Block 2nd Block 3rd Block 4th Block 5th Block Data Storage in Strip Memory
1st Line Data
2nd Line Data
7th Line Data
8th Line Data
A Memory
MADD 0 $20 $40 $60 $80
0
0Y 1 0Y 9 0U 1 0V 1 0Y17
1
0Y 3 0Y11 0U 3 0V 3 0Y19
2
0Y 5 0Y13 0U 5 0V 5 0Y21
3
0Y 7 0Y15 0U 7 0V 7 0Y23
4
1Y 1 1Y 9 1U 1 1V 1 1Y17
5
1Y 3 1Y11 1U 3 1V 3 1Y19
6
1Y 5 1Y13 1U 5 1V 5 1Y21
19
6Y 3 6Y11 6U 3 6V 3 6Y19
1A
6Y 5 6Y13 6U 5 6V 5 6Y21
1B
6Y 7 6Y15 6U 7 6V 7 6Y23
1C
7Y 1 7Y 9 7U 1 7V 1 7Y17
1D
7Y 3 7Y11 7U 3 7V 3 7Y19
1E
7Y 5 7Y13 7U 5 7V 5 7Y21
1F
7Y 7 7Y15 7U 7 7V 7 7Y23
1st Block 2nd Block 3rd Block 4th Block 5th Block
Note: aYb notation indicates the Y component of the pixel element in row "a" and column "b".
Figure 22. Memory Format - MODE 1:0 = 01
17
PRELIMINARY
ZR36015
Pixel Data <15:8> Pixel Data <7:0> Odd Line Memory Data <15:8> Memory Data <7:0> Even Line Memory Data <15:8> Memory Data <7:0> Strip Memory MADD 0 $20 $40 $60 $80 $A0 $C0 0
0Y 0 0Y 8 8Y 0 8Y 8 0U 0 1V 0 0Y16 0Y 0 0U 0 0Y 0 0Y 1 1Y 0 1Y 1 0Y 2 0Y 3 1Y 2 1Y 3 0Y 1 0V 0 0Y 4 0Y 5 1Y 4 1Y 5 0Y 2 0U 1 0Y 6 0Y 7 1Y 6 1Y 7 0Y 3 0V 1 0U 0 0U 1 1V 0 1V 1 0Y 4 0U 2 0U 2 0U 3 1V 2 1V 3 0Y 5 0V 2 0Y 8 0Y 9 1Y 8 1Y 9 0Y 6 0U 3 0Y10 0Y11 1Y10 1Y11 0Y 7 0V 3 0U 4 0U 5 1V 4 1V 5 0Y 8 0U 4 0U 6 0U 7
Data Sequence on Pixel Bus
Data Sequence on Memory Data Bus
1V 6 1V 7
1
0Y 2 0Y10 8Y 2 8Y10 0U 2 1V 2 0Y18
2
0Y 4 0Y12 8Y 4 9Y12 0U 4 1V 4 0Y20
3
0Y 6 0Y14 8Y 6 8Y14 0U 6 1V 6 0Y22
4
1Y 0 1Y 8 9Y 0 9Y 8 2U 0 3V 0 1Y16
5
1Y 2 1Y10 9Y 2 9Y10 2U 2 3V 2 1Y18
1A
6Y 4 6Y12 14Y4 12U4 13V4 6Y20
1B
6Y 6 6Y14 14Y6 12U6 13V6 6Y22
1C
7Y 0 7Y 8 15Y0 13U0 15V0 7Y16
1D
7Y 2 7Y10 15Y2 13U2 15V2 7Y18
1E
7Y 4 7Y12 15Y4 13U4 15V4 7Y20
1F
7Y 6 7Y14 15Y6 13U6 15V6 7Y22
A Memory
14Y12 14Y14 15Y8 15Y10 15Y12 15Y14
1st Block 2nd Block 3rd Block 4th Block 5th Block 6th Block 7th Block Data Storage in Strip Memory
B Memory
MADD 0 $20 $40 $60 $80 $A0 $C0
0
0Y 1 0Y 9 8Y 1 8Y 9 0U 1 1V 1 0Y17
1
0Y 3 0Y11 8Y 3 8Y11 0U 3 1V 3 0Y19
2
0Y 5 0Y13 8Y 5 9Y13 0U 5 1V 5 0Y21
3
0Y 7 0Y15 8Y 7 8Y15 0U 7 1V 7 0Y23
4
1Y 1 1Y 9 9Y 1 9Y 9 2U 1 3V 1 1Y17
5
1Y 3 1Y11 9Y 3 9Y11 2U 3 3V 3 1Y19
1A
6Y 5 6Y13 14Y5 12U5 13V5 6Y21
1B
6Y 7 6Y15 14Y7 12U7 13V7 6Y23
1C
7Y 1 7Y 9 15Y1 13U1 15V1 7Y17
1D
7Y 3 7Y11 15Y3 13U3 15V3 7Y19
1E
7Y 5 7Y13 15Y5 13U5 15V5 7Y21
1F
7Y 7 7Y15 15Y7 13U7 15V7 7Y23
14Y13 14Y15 15Y9 15Y11 15Y13 15Y15
1st Block 2nd Block 3rd Block 4th Block 5th Block 6th Block 7th Block
Note: aYb notation indicates the Y component of the pixel element in row "a" and column "b".
Figure 23. Memory Format - MODE 1:0 = 10
Pixel Data <15:8> Pixel Data <7:6> Pixel Data <5:4> Memory Data <15:8> Memory Data <7:0> Strip Memory MADD 0 $20 $40 $60 $80 $A0 $C0
0Y 0 0Y 1
0Y 0 0U 1 0V 1 0Y 2 0Y 3
0Y 1 0U 2 0V 2 0Y 4 0Y 5
0Y 2 0U 3 0V 3 0Y 6 0Y 7
0Y 3 0U 4 0V 4 0U 0 0U 1
0Y 4 0U11 0V11 0V 0 0V 1
0Y 5 0U12 0V12 0Y 8 0Y 9
0Y 6 0U13 0V13 0Y10 0Y11
0Y 7 0U14 0V14 0Y12 0Y13
0Y 8 0U21 0V21 0Y14 0Y15 0U 2 0U 3 0V 2 0V 3
Data Sequence on Pixel Bus
Data Sequence on Memory Data Bus
0
0Y 0 0Y 8 0Y16 0Y24 0U 0 0V 0 8Y32
1
0Y 2 0Y10 0Y18 0Y26 0U 2 0V 2 8Y34
2
0Y 4 0Y12 0Y20 0Y28 0U 4 0V 4 8Y36
3
0Y 6 0Y14 0Y22 0Y30 0U 6 0V 6 8Y38
4
1Y 0 1Y 8 1Y16 1Y24 1U 0 1V 0 9Y32
5
1Y 2 1Y10 1Y18 1Y26 1U 2 1V 2 9Y34
1A
6Y 4 6Y12 6Y20 6Y28 6U 4 6V 4
1B
6Y 6 6Y14 6Y22 6Y30 6U 6 6V 6
1C
7Y 0 7Y 8 7Y16 7Y24 7U 0 7V 0
1D
7Y 2 7Y10 7Y18 7Y26 7U 2 7V 2
1E
7Y 4 7Y12 7Y20 7Y28 7U 4 7V 4
1F
7Y 6 7Y14 7Y22 7Y30 7U 6 7V 6
A Memory
14Y36 14Y38 15Y32 15Y34 15Y36 15Y38
1st Block 2nd Block 3rd Block 4th Block 5th Block 6th Block 7th Block Data Storage in Strip Memory
B Memory
MADD 0 $20 $40 $60 $80 $A0 $C0
0
0Y 1 0Y 9 0Y17 0Y25 0U 1 0V 1 8Y33
1
0Y 3 0Y11 0Y19 0Y27 0U 3 0V 3 8Y35
2
0Y 5 0Y13 0Y21 0Y29 0U 5 0V 5 8Y37
3
0Y 7 0Y15 0Y23 0Y31 0U 7 0V 7 8Y39
4
1Y 1 1Y 9 1Y17 1Y25 1U 1 1V 1 9Y33
5
1Y 3 1Y11 1Y19 1Y27 1U 3 1V 3 9Y35
1A
6Y 5 6Y13 6Y21 6Y29 6U 5 6V 5
1B
6Y 7 6Y15 6Y23 6Y31 6U 7 6V 7
1C
7Y 1 7Y 9 7Y17 7Y25 7U 1 7V 1
1D
7Y 3 7Y11 7Y19 7Y27 7U 3 7V 3
1E
7Y 5 7Y13 7Y21 7Y29 7U 5 7V 5
1F
7Y 7 7Y15 7Y23 7Y31 7U 7 7V 7
14Y37 14Y39 15Y33 15Y35 15Y37 15Y39
1st Block 2nd Block 3rd Block 4th Block 5th Block 6th Block 7th Block
Note: aYb notation indicates the Y component of the pixel element in row "a" and column "b".
Figure 24. Memory Format - MODE 1:0 = 11
18
PRELIMINARY
ZR36015
Strip Buffer Capacity
The address range for the strip buffer is 64K (limited by the number of address bits for the strip buffer memory). Given that the strip buffer is 16 bits wide, this gives a maximum memory capacity of 128K bytes that can be accessed. The raster to block process stores even blocks for each element in the A strip buffer memory, and the odd blocks for each element in the B strip bufer memory (see figure TBD). This divides the storage capacity required for the total strip evenly between the A and B sides of the memory. The table below is used to calculate the required total strip buffer memory capacity (evenly distributed between the A and B memories) of the strip buffer. Capacity = 2 x K x L x HWidth x D Where... s "2" is required because the strip buffer is double buffered s K indicates the number of bytes of data required for each pixel s L indicates the number of lines of data required to form a strip s D is equal to "1" for no decimation delected, and is equal to "1/2" if decimation is selected. The maximum number of pixels per line that can be entered for each mode is given in the table below. This number for the maximum number of pixels per line is determined by the maximum addressable strip buffer capacity. When less strip memory is used (i.e., less than 64K x 16-bits), then the numbers in the table below must be scaled accordingly. The limitations for the VHeight values are given in the table below. These limitations are imposed so that the image size corresponds to a complete Minimum Configurable Unit (as defined in the JPEG specification)
MOD (1:0) k 1 0 (1:0:0) 1 8 1 4:2:2) 2 8 2 (4:1:1) 1.5 16 3 (4:1:1) 1.5 8 MOD (1:0) HWidth maximum value
(Maximum number of pixels in horizontal direction)
0 (1:0:0) 16384
1 (4:2:2) 8192
2 (4:1:1) 5440
3 (4:1:1) 10880
DCM = 1
HWidth minimum value
(Minimum number of pixels in horizontal dirction)
16 Multiple of 16
32 Mulitple of 32
32 Multiple of 32
64 Multiple of 64
Setting value of HWidth
The limitations to PAY are such that the maximum value is 8192 lines and the minimum value for each format is as shown below:
MOD (1:0) VWIdth minimum value
(Minimum number of lines in vertical direction)
0 (1:0:0) 8 Multiple of 8
1 4:2:2) 8 Multiple of 8
2 (4:1:1) 16 Multiple of 16
3 (4:1:1) 8 Multiple of 8
Setting value of VWIdth
Coder Bus Interface
The ZR36015 Raster to Block Converter interfaces directely to the ZR36050 JPEG Codec. The Coder Bus Interface consists of the DSYNC, BDATA(7:0), STOP, EOS, and COE signals (see figure 2). The Direction of these interface for each mode of operation is given in the table below. Table 5: Coder Bus Interface
Signal DSYNC BDATA (7:0) STOP EOS COE Compression Mode (EDC = 0) Output Output Input Output Input Expansion Mode (EDC = 1) Input Input Output Input Input
HWidth is limited as shown below:
MOD (1:0) HWidth maximum value
(Maximum number of pixels in horizontal direction)
0 (1:0:0) 8192
1 (4:2:2) 4096
2 (4:1:1) 2720
3 (4:1:1) 5440
The data transfer rate on BDATA(7:0) is equal to the SYSCLK rate for all formats. The mode of operation is determined by the "EDC" bit in the Mode Register when the GO bit is asserted. Bidirectional signals are availiable as inputs immediately after a hard reset, and as outputs after the GO bit in the Mode Register has been set. The COE signal enables the outputs of the bidirectional signals of the Code Bus Interface. When COE is High, the outputs for Compression Mode are enabled, when COE is Low, the output for Expansion mode are enabled. When the ZR36015 is used
DCM = 0
HWidth minimum value
(Minimum number of pixels in horizontal dirction)
8 Multiple of 8
16 Multiple of 16
16 Multiple of 16
32 Multiple of 32
Setting value of HWidth
19
PRELIMINARY
ZR36015
with the ZR36050, the COE signal is connected to the ZR36050's "COMP" output. The DSYNC signal synchronized 64 byte block transfers between the ZR36015 and the ZR36050. The STOP signal indicates to the sending device that the receiving device is not ready for more data. New blocks of data will not be sent to the receiving device until the STOP signal becomes inactive. The EOS signal indicates the end of each component of a scan. This active low signal is an output in encoding modes. EOS indicates the last image data sample of the last block of each scan leaving the ZR36015. In encoding modes, EOS is output regardless of the STOP signal. EOS is an input signal in the decoding mode. It is input together with the last image data sample of the last block of each scan entering the ZR36015. The width of EOS is one SYSCLK cycle in encoding mode, and must be on SYSCLK cycle in decoding mode. Figure 22 shows the functional timing for the DSYNC and EOS signals relative to the BDATA(7:0) data and SYSCLK. The functional timing relationship for the STOP (when used as an input during compression mode) is given in Figure 23.
SYSCLK DSYNC BDATA (7:0) 1 2 3 4 5 6 61 62 63 64 1 2 3
DSYNC EOS BDATA (7:0) 64 1 2 3 4 5 6 61 62 63 64
Figure 25. Functional Timing for DSYNC and EOS Relative to BDATA(7:0)
SYSCLK DSYNC BDATA (7:0) STOP If STOP is low, do not output DSYNC If STOP is High, output DSYNC 62 63 0 1 2 3 4 59 60 61 62 63
Figure 26. Functional Timing for STOP When Used as an Input The "delay to memory write" indicates the number of clock cycles it takes for the pixel data to propagate through the ZR36015 to the strip buffer memory. This value is shown in the table below. Table 6: Delay to Memory Write
Mode 0 1 2 3 Delay (in number of SYSCLKS) 2 or 3 10 or 11 10 or 11 10 or 11
In the table above, the smaller value corresponds to the even clock PXDATA element, and the larger value corresponds to the odd PXDATA element (the ZR36015 writes 16 bits to the strip memroy at a time).
20
PRELIMINARY
ZR36015
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................................... -55C to +125C Storage Temperature ........................................ -40C to +125C Supply Voltage to Ground Potential Continuous...................................... -0.5V to VCC+0.5V DC Voltage Applied to Outputs for High Impedance Output State ....................... -0.3V to VCC+0.3V DC Input Voltage ............................................ -0.5V to VCC+0.5V DC Output Current, into or out of Outputs (not to exceed 200mA total) ................................... 20mA/output DC Input Current ............................................................. 10mA
NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
OPERATING RANGE
Commercial Devices
Temperature.....................................................0C TA +70C Supply Voltage ........................................... 4.75V VCC 5.25V
DC CHARACTERISTICS
Symbol VIL VIH VOL Input Low Voltage Input High Voltage Output Low Voltage Parameter Min - 2.0 Max 0.8 - 0.4 VSS + 0.05 VOH Output High Voltage 2.4 VDD - 0.05 ICC ILI ILO IOZ CIN CB VII Power Supply Current TBD Units V V V V V V mA A A A pF pF V IOL = 8mA IOL = 1A IOH = -8mA IOH = -1A VDD = 5V, f=30 MHz, CL=20pf, TA=25C VIN = VDD VOUT = VSS VOUT = VDD or VSS Test Conditions
Input Leakage Current Output Leakage Current Output Disable Current Input Capacitance Bidirectional Capacitance Hysteresis Voltage
-TBD -TBD -TBD
TBD TBD TBD TBD TBD
TBD
21
PRELIMINARY
ZR36015
AC CHARACTERISTICS
Signal Number 1 2 3 4 5 6 7 8 9 CLK Period CLK High Clock Low Width Clock Rise Time Clock Fall Time Input Hold Time1 Description Min 33 15 15 3 3 5 5 PIXDATA2 4 2 5 2 33 24 ns Data Propagation Delay for CLKCSC 10 Data Propagation Delay for DSYNC, STOP, EOS, COE, BDATA RESET Pulse Width Data Propagation Delay for WINDOW Data Propagation Delay for PIXDATA3 Memory Write Address Set-up Memory Write Address Hold4 Memory Write Pulse5 16 17 ns Max Units ns ns ns ns ns ns ns ns tbd 2.0V Test Conditions
Input Setup Time1 Data Propagation Delay for
Data Propagation Delay for CBUSY, WINDOW, BSY
11 12 13 18 19 21 22 23 24 27 28 30 33 34 35 36 37 40 41 50 51 52
tbd 2 4 tbd 1 21 tbd tbd 5 tbd tbd tbd tbd tbd tbd tbd tbd 2 2 tbd tbd tbd 23 23 24 33
ns ns ns ns ns ns ns ns ns ns nd ns ns ns ns ns ns ns ns ns ns ns
Memory Output Disable to End of Write Memory Write Data Valid6
Memory Write Data Hold4 Memory Data High-Z Time Memory Data Enable Time Memory Read Cycle Memory Output Enable Pulse Width (Low) Memory Read Data Setup Memory Read Data Hold Memory Read Address Valid Memory Read Address Hold Propagation Delay for MWE Propagation Delay for MOE Time before Trailing SPH that RD, WR Should be High Minimum Host Write Pulse Width Minimum Host Read Pulse Width
22
PRELIMINARY
ZR36015
Signal Number 53 54 55 56 58 59 60 61 62 63 64 70 1. 2. 3. 4. 5. 6. Host Address Setup Host Address Hold Minimum Non-Active Time Between Host Read or Write Minimum Time After Fall of SPH to 1st Read or Write Host Read Address Hold Time Host Write Data Valid Host Write Data Hold Host Read Data Enable Host Read Data Valid Host Read Data Hold Host Read Data Disable Propagation Delay for CSCCLK Description Min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd Max Units ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions
TIH and TIS are for the following input signals: PXDATA (15:0), HEN, VEN, DSYNC, STOP, EOS, BDATA Assumes WINDOW signal is high. Measured during clock cycle when WINDOW goes high. Measured from either rise of MWE, or fall of MOE. Time during which MWE = low, and MOE = high. Measured from start of time when MWE = low, and MOE = High.
2.0V
INPUT
0.45V
1.5V
DEVICE UNDER TEST
1.5V
OUTPUT
From Output Under Test
50pF
Test Point
A.C. testing, inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input and output timing measurements are made a t 1.5V for both logic "1" and "0".
Figure 1. AC TESTING INPUT, OUTPUT
Figure 1. NORMAL AC TEST LOAD
1 2 2.0V 1.5V 0.8V 5 3 2.0V 1.5V 0.8V 4 RESET 11
SYSCLK
Figure 1. System Clock Timing
Figure 1. RESET Pulse Width
23
PRELIMINARY
ZR36015
SYSCLK 6 INPUT 7 OUTPUT SYSCLK 9 10
Figure 1. Synchronous Input Setup & Hold Times
Figure 1. Output Propogation Delay
12 SYSCLK
12
WINDOW
13 PIXDATA Data 0
8 Data 1 Data n
8
Figure 1. X4
24
PRELIMINARY
ZR36015
SYSCLK
40 MWE
40
41 MOE
41
Figure 1. Memory Interface Synchronous Timing
SYSCLK
18 MADDR Write Address
19
30 Read Address
40 MWE 41
21
33 27 37
MOE
28 23 24 Write Data 35 34
MDATA (OUT)
MDATA (IN)
Read Data
Figure 1. Memory Interface R/W Asynchronous Timing
SPH
53 ADDR 50 56 WR 51 Write Address
54 Write Address Read Address
58
55
52 RD 59 60 PXDATA (7:0) Write Data Write Data 61 62 63 64
Figure 1. System Interface Timing
SYSCLK 9 CSCCLK
SYSCLK 9 CSCCLK
Figure 1. 203CLK Timing - Mode = 0
Figure 1. 203CLK Timing - Mode = 1, 2, 3
25
PRELIMINARY
ZR36015
100-Pin Flat Pack Pin Assignment
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name GND CLKCSC VCC VEN HEN GND PXDATA15 PXDATA14 PXDATA13 PXDATA12 PXDATA11 PXDATA10 PXDATA9 PXDATA8 GND VCC PXDATA7 PXDATA6 PXDATA5 PXDATA4 Type - O - I I B B B B B B B B B B B B Pin No 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name PXDATA3 PXDATA2 PXDATA1 PXDATA0 GND SYSCLK VCC ADD1 ADD0 SPH WR RD BSY CBSY WINDOW VCC GND MADD0 MADD1 GND Type B B B B - I - I I I I I O O O O O - Pin No 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name VCC MADD2 MADD3 MADD4 MADD5 MADD6 MADD7 MADD8 MADD9 GND VCC MADD10 MADD11 MADD12 MADD13 MADD14 MADD15 GND MDATA0 MDATA1 Type - O O O O O O O O - - O O O O O O O O Pin No 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name MDATA2 MDATA3 MDATA4 MDATA5 MDATA6 GND VCC MDATA7 MDATA8 MDATA9 MDATA10 MDATA11 MDATA12 MDATA13 MDATA14 GND MDATA15 MOE MWE VCC Type O O O O O - - O O O O O O O O - O O O - Pin No 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name GND BDATA0 BDATA1 BDATA2 BDATA3 BDATA4 BDATA5 BDATA6 BDATA7 GND VCC NC COE DSYNC STOP EOS GND RESET NC VCC Type B B B B B B B B - - O B B B I - -
GND CLKCSC VCC VEN HEN GND PXDATA15 PXDATA14 PXDATA13 PXDATA12 PXDATA11 PXDATA10 PXDATA9 PXDATA8 GND VCC PXDATA7 PXDATA6 PXDATA5 PXDATA4 PXDATA3 PXDATA2 PXDATA1 PXDATA0 GND SYSCLK VCC ADD1 ADD0 SPH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VCC NC RESET GND EOS STOP DSYNC COE N.C. VCC VSS BDATA7 BDATA6 BDATA5 BDATA4 BDATA3 BDATA2 BDATA1 BDATA0 VSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VCC MWE MOE MDATA15 GND MDATA14 MDATA13 MDATA12 MDATA11 MDATA10 MDATA9 MDATA8 MDATA7 VCC GND MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 GND MADD15 MADD14 MADD13 MADD12 MADD11 MADD10 VCC
WR RD BSY CBSY WINDOW VCC GND MADD0 MADD1 GND VCC MADD2 MADD3 MADD4 MADD5 MADD6 MADD7 MADD8 MADD9 GND
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
26
PRELIMINARY
ZR36015
ORDERING INFORMATION
ZR 36015 PQ C -30
PACKAGE PQ - Plastic Quad Flat Pack (EIAJ) DATA CLOCK RATE SCREENING KEY PACKAGE PART NUMBER PREFIX DATA CLOCK RATE 30.0 MHz SCREENING KEY C - 0C to +70C (VCC = 4.75V to 5.25V)
SALES OFFICES
s U.S. Headquarters Zoran Corporation 1705 Wyatt Drive Santa Clara, CA 95054 USA Telephone: 408-986-1314 FAX: 408-986-1240 s Israel Design Center Zoran Microelectronics, Ltd. Advanced Technology Center P.O. Box 2495 Haifa, 31024 Israel Telephone: 972-4-551-551 FAX: 972-4-551-550 s Japan Operations Zoran Corporation 1-5-3 Ebisu Kogetsu Bldg. 4th Floor Shibuya-Ku, Tokyo Japan Telephone: 81-3-3448-1980 FAX: 81-3-3448-1690
The material in this data sheet is for information only. Zoran Corporation assumes no responsibility for errors or omissions and reserves the right to change, without notice, product specifications, operating characteristics, packaging, etc. Zoran
Corporation assumes no liability for damage resulting from the use of information contained in this document.
DS36015-0693

▲Up To Search▲

Price & Availability of ZR36015

	To Download ZR36015 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .